QpiAI Achieves High Speed Quantum Error Correction on Superconducting Systems with New Decoder Platform

BusinessWire India
Bangalore (Karnataka) [India], March 25: A scalable quantum error correction system has been developed by QpiAI to enable fast, scalable error correction using a rotated surface code architecture. The decoder, based on a union-find algorithm, is designed to operate in real time alongside superconducting qubits and represents a key step toward practical fault-tolerant quantum computing.
The system implements a distance-5 rotated surface code using 49 physical qubits. Each decoder instance runs on a single QpiAI Kaveri QPU, which provides 64 qubits, allowing one decoder instance per chip. The architecture is optimized to support efficient decoding and integration with existing quantum hardware.

QpiAI Founder and CEO Dr Nagendra suggested, "The design of QpiAI QEC for 64 qubit Kaveri QPU is a promising development towards large scale Quantum computing deployment. With this setup we would like to prove Error correction and reduction in errors possible and eventually lead to fault tolerant Quantum computing. QpiAI FTQC will lead us to many advances in pharmaceutical, chemicals, manufacturing and climate modelling. QpiAI is excited for this to be demoed soon. Further current QEC is capable of being used on transmon qubits. We will be implementing next generation of QEC for QpiAI Qubits (Fluxonium variant) and distributed QEC to be used across QPUs."
Vamsi Krishna, VP of Digital Hardware, said, "Roadmap for QpiAI QEC would be to develop robust quantum error correction codes and Decoders including qLDPC to optimise on the number of physical qubits and to achieve two logical qubit gates using QEC. While current state-of-the-art QEC decoder for distance 5 surface codes runs at 60 microsecond latency and runs on CPUs and GPUs, we were able to achieve end to end latency of 1.5 microsecond and decoder only latency of less than 1 microsecond. This is very significant latency reduction on a purpose built hardware. This is version 1 of QEC decoder. In next version we will add distance 7 surface code support and qLDPC. As decoder support for various QEC configuration stabilizes we plan to fabricate the QEC processor in advanced process node to reduce footprint and power consumption."
Dr Manjunath R V, VP and GM for Quantum Hardware, added, "QpiAI Quantum processors have error-correction architecture as foundational design principle with optimised superconducting quantum processor layout and fabrication. Leveraging QpiAI fast-decoder platform with QpiAISense quantum control electronics enables scalable development of quantum processors towards fault-tolerant quantum computing at QpiAI."

Significant Milestone for Indian National Quantum Mission (NQM)
Indian NQM invested in QpiAI to design 64 qubit Kaveri QPU. NQM has significant Milestone at hand. Dr Abhay Karandikar, Secretary of Department of Science and Technology (DST), Government of India, suggested, "Quantum Error Correction (QEC) is essential for scalable quantum computing. By implementing distance 5 surface code QEC in custom hardware rather than traditional CPUs, QpiAI is accelerating the deployment of its 64-qubit Kaveri QPU in India, marking a major step toward practical, large-scale quantum utility. From National Quantum Mission, we are excited with this development."
Each error-correction cycle completes in approximately 1.5 microseconds. To account for measurement errors, the system performs five rounds of stabilizer measurements per correction cycle, ensuring robust detection and correction of both qubit and measurement faults.
The qubit coherence times in 64 qubit Kaveri are promising, with T1 times around 100 microseconds and T2 times around 95 microseconds, providing sufficient headroom for multiple error-correction cycles within the coherence window.
At the core of the system is a compact hardware decoder capable of completing decoding for a distance-5 rotated surface code in a maximum of 40 clock cycles. The design is intentionally lightweight and scalable: the current platform can accommodate up to 20 decoders simultaneously, enabling parallel error-correction across multiple logical qubits. Future systems with larger FPGA resources will allow deployment of additional decoders or support for higher-distance surface codes.
Active correction capabilities are currently being implemented to allow real-time correction of qubits on the fly, further reducing accumulated error rates. The decoder already supports Pauli errors and measurement errors, making it suitable for realistic quantum noise environments.
The Kaveri QPU architecture has been specifically designed to be surface-code friendly, with qubit connectivity tailored for efficient stabilizer measurement and decoding. In parallel, additional qubit connectivity architectures are being explored to support more efficient decoding strategies and higher-performance error-correction schemes.
The current setup uses simulated qubits to validate the decoding pipeline and system performance. Integration with physical qubits and experimental results from running the decoder alongside connected qubits in 64 qubit Kaveri QPU are under development.
This development demonstrates a practical pathway toward scalable, hardware-accelerated quantum error correction -- a critical requirement for building reliable, large-scale quantum computers.
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